In the fabrication process for semiconductor devices, numerous fabrication steps, as many as several hundred, must be executed on a silicon wafer in order to complete integrated circuits on the wafer. Generally, the process for manufacturing integrated circuits on a silicon wafer substrate typically involves deposition of a thin dielectric or conductive film on the wafer using oxidation or any of a variety of chemical vapor deposition processes; formation of a circuit pattern on a layer of photoresist material by photolithography; placing a photoresist mask layer corresponding to the circuit pattern on the wafer; etching of the circuit pattern in the conductive layer on the wafer; and stripping of the photoresist mask layer from the wafer.
Prior to deposition of the conductive and insulative layers on a wafer, the wafer is typically subjected to a polishing operation to provide an extremely level starting surface on the wafer. During the subsequent structuring of the substrate, the various processing steps are used to build up the layers of conductors and dielectrics, for example, on which other layers are formed to fabricate the circuits. With structuring becoming ever finer, the associated replication processes are becoming more sensitive to surface variations on the substrate. Therefore, it has now become necessary to “re-level” the wafer surface even while production of the integrated circuits are in progress. The re-leveling operation is referred to as planarizing and is typically accomplished using the CMP (chemical mechanical planarization) method using a chemical mechanical polishing process.
In chemical mechanical polishing, an abrasive suspension agent or slurry is dispensed onto a polishing surface. Relative movement between the polishing surface and the wafer produces a combined mechanical and chemical effect on the surface of the wafer. This process creates a highly level surface on the wafer. In order to remove the still-moist remains of slurry, as well as small surface defects which may remain in the wafer and disrupt the otherwise planar continuity of the wafer surface after the CMP process, post-CMP cleaning steps are required.
One of the cleaning steps carried out after the chemical mechanical polishing process is facilitated using rotating scrubber brushes which are actuated inside a scrubber cleaner. Accordingly, a special washing fluid and a rotational movement with multiple pairs of scrubber brushes can clean both sides of the wafer using contact pressure against the wafer. Because the wafer becomes considerably more valuable with each successive planarizing operation, the post-CMP brush cleaning operation is commercially significant.
One of the most common post-CMP scrubber cleaners used to remove residues from a wafer substrate after a CMP operation is the Dai Nippon Screen (DNS) brush scrubber cleaner. The DNS brush scrubber cleaner cleans wafers using a combination of rinsing, megasonic rinsing, and brush cleaning. The wafer substrates, having been previously subjected to chemical mechanical planarization, are loaded into a wet environment, typically water, and then transported through a series of cleaning chambers for the brush cleaning cycle. The brush cleaning cycle involves rotating the wafer at high speed, typically about 1500 rpm, while a jet of deionized water is sprayed on the wafer to dislodge any loose debris from the CMP process. Simultaneously, the wafer is brushed with a foam brush.
In addition to being used to clean wafers after a CMP process, the DNS scrubber cleaning method is used to remove metal particles from trenches and vias after a metal seed layer has been deposited in the trenches and vias typically using a dual damascene process. A typical dual damascene structure 10 is shown in FIG. 1 and includes a metal line 14 formed in a substrate 12. A bottom dielectric layer 16 is deposited on the substrate 12. A top dielectric layer 18 is deposited on the bottom dielectric layer 16. A via opening 20 is etched in the bottom dielectric layer 16, and a trench opening 22 is etched in the top dielectric layer 18, over the via opening 20.
A metal barrier layer 24 is deposited over the sidewalls of the trench opening 22 and over both the sidewalls and bottom of the via opening 20. A metal seed layer 26, typically copper, is deposited over the barrier layer 24. Finally, copper (not shown) is deposited in the via opening 20 and the trench opening 22, on the seed layer 26, using CVD (chemical vapor deposition) or metal electroplating techniques.
In the dual damascene process, particles 28 sometimes fall from the environment or from the seed layer 26, onto the bottom of the via opening 20 and/or trench opening 22. These particles 28 adversely affect the Rs and Rc performance of the metal interconnects formed in the via opening 20 and trench opening 22. Accordingly, the DNS scrubber cleaning method is frequently used to remove particulate contaminants from a via opening and/or a trench opening after formation of a seed layer in the opening and prior to electroplating the metal interconnects in the via opening and trench opening.
One of the limitations of the scrubber cleaning method to remove particulate contaminants from via openings in a damascene structure is that the method is ineffective in the removal of particles from via and trench openings having a width of less than about 0.2 μm. Consequently, the particles often remain in the openings upon subsequent electroplating of the metal interconnects, compromising the functional integrity of the interconnects in the finished IC device. Accordingly, a novel method is needed for the removal of particles from via openings and/or trench openings formed on a substrate, particularly via openings and trench openings having a width of less than about 0.2 μm.
An object of the present invention is to provide a novel method which is suitable for cleaning a substrate.
Another object of the present invention is to provide a novel method which is suitable for removing metal particles from via openings and/or trench openings in a substrate.
Still another object of the present invention is to provide a novel electropolishing cleaning method which is potentially capable of enhancing the Rc and Rs performance of IC devices fabricated on a semiconductor substrate.
Yet another object of the present invention is to provide an electropolishing cleaning method which utilizes a novel electrolyte solution to both remove defects from a seed layer deposited in trench and via openings and dissolve or remove potential device-contaminating particles remaining on the seed layer.
A still further object of the present invention is to provide a novel electropolishing cleaning method which is applicable to cleaning via and/or trench openings of various sizes on a wafer.
Yet another object of the present invention is to provide a novel electropolishing cleaning method which utilizes a combination of a rotational mechanical force and a series of electrical pulses or a continuous electrical pulse to remove defects from a seed layer in via and/or trench openings and dissolve or remove potential device-contaminating particles remaining on the seed layer.